Hardware implementation of the Totally Self-Checking SHA-256 hash core

Abstract

Hashing cores are utilized by many existing high performance cryptographic systems, used in security schemes such as SET, PKI, and IPSec. Efficient operation of these hardware modules can be degraded, especially when they operate in harsh environments i.e. space applications, military or medical applications. In this paper, a Totally Self-Checking (TSC) design is introduced for the SHA-256 hash function, suitable for harsh environments. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even number of erroneous bits, if they are appropriately propagated. Performance measurements are reported for ASIC and reconfigurable technologies, highlighting issues that must be respected by the designer. The introduced TSC hashing core is area-efficient by 19%, compared to the corresponding Duplicated with Checking (DWC) one.