Please use this identifier to cite or link to this item:
https://hdl.handle.net/20.500.14279/33229
Title: | Deep p-Ring Trench Termination: An Innovative and Cost-Effective Way to Reduce Silicon Area | Authors: | Antoniou, M. Lophitis, Neophytos Udrea, F. Rahimo, M. Vemulapati, U. Corvasce, C. Badstuebner, U. |
Major Field of Science: | Engineering and Technology | Keywords: | high voltage;Power semiconductor devices;termination | Issue Date: | 1-Feb-2019 | Source: | IEEE Electron Device Letters, 2019, vol. 40, iss. 2, pp. 177 - 180 | Volume: | 40 | Issue: | 2 | Start page: | 177 | End page: | 180 | Journal: | IEEE Electron Device Letters | Abstract: | A new type of high-voltage termination, namely the 'deep p-ring trench' termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the traditional p+ ring-type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide, which results in reduced hot carrier injection and improved device reliability. | URI: | https://hdl.handle.net/20.500.14279/33229 | ISSN: | 07413106 | DOI: | 10.1109/LED.2018.2890702 | Rights: | Attribution-NonCommercial-NoDerivatives 4.0 International | Type: | Article | Affiliation : | University of Warwick Coventry University University of Cambridge ABB Switzerland Ltd., Semiconductors |
Publication Type: | Non Peer Reviewed |
Appears in Collections: | Άρθρα/Articles |
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