High performance pipelined FPGA implementation of the SHA-3 hash algorithm
Date Issued
August 6, 2015
Abstract
The SHA-3 cryptographic hash algorithm is standardized in FIPS 202. We present a pipelined hardware architecture supporting all the four SHA-3 modes of operation and a high-performance implementation for FPGA devices that can support both multi-block and multi-message processing. Experimental results on different FPGA devices validate that the proposed design achieves significant throughput improvements compared to the available literature.
Affiliation
Funding
EUROMICRO,Faculty of Electrical Engineering of the University of Montenegro,IEEE,MANT,Ryazan State Radio Engineering University