High-performance FPGA implementations of the cryptographic hash function JH
Journal
IET Computers and Digital Techniques
Date Issued
January 2013
DOI
10.1049/iet-cdt.2012.0070
Abstract
Hash functions are included in almost all cryptographic schemes and security protocols for providing authentication services. JH is a new hash function, introduced in 2008 and it is among the five finalists of the international competition for developing the new hash standard SHA-3. In this study, one non-pipelined and four pipelined architectures are introduced for developing high-performance field-programmable gate array (FPGA) designs of the JH function. Special effort has been paid and various design alternatives have been studied to derive efficient FPGA implementations in terms of frequency, area and throughput/ area cost factor. Compared with the best existing non-pipelined FPGA implementations, the throughput/area is improved by 48, 13.5 and 17.8% in Xilinx Virtex-4, Virtex-5 and Virtex-6 families, respectively, and by 6.8 and 21.2% in ALTERA Stratix-III and Stratix-IV, respectively. Also, the improvements of the throughput/area factor of the introduced pipelined architectures over the existing ones are 37.5, 73.1, 15 and 26.3% in Virtex-5, Virtex-6, Stratix-III and Stratix-IV technologies, respectively.