Optimization of the buffer layer in a 15kV SiC N-type gate commutated thyristor for safe, low-loss switching
Journal
Power Electronic Devices and Components
Date Issued
June 25, 2025
DOI
10.1016/j.pedc.2025.100099
Abstract
This paper explores the design and optimization of the buffer layer in Silicon Carbide (SiC) N-type Gate Commutated Thyristors (GCTs) to enhance low-loss switching and ensure safe operation in ultra high-voltage (over 10 kV) applications. The challenges posed by high dv/dt conditions during turn-off are known to cause snappy behaviour and high reverse current spikes through the cathode, which degrades switching reliability. Using Synopsys Technology Computer Aided Design (TCAD) models, validated against experimental data, the impact of the device design on the switching performance is investigated. By employing a carefully calibrated three-stage buffer design, we significantly reduce the high dv/dt which in turn is shown to alleviate the reverse cathode current caused by snap off effect. Furthermore, switching losses are reduced without substantially impacting the blocking voltage or the on-state voltage drop. Comparing the performance of the proposed design with conventional single buffer designs, the new GCT design demonstrates improved performance in terms of dv/dt control and energy loss during IGCT turn-off (31.8 % and 33.6 % respectively), in exchange for a 3.06 % increase in conduction losses. The results confirm that our proposed ”3-step buffer” design not only suppresses the snap off phenomenon but also extends the applicability of SiC IGCTs to broader high-power switching applications.
Subjects