Digit-Serial IIR Filter Implementation on FPGA
Date Issued
1998
Author(s)
Abstract
This project is based on the implementation of a digit-serial Iffi filter, on FPGA by
either using VHDL or ECAD programs (Viewlogic).
The application of the digit-serial structures to the design of IIR filters introduces
delay elements in the feed back loop of the HR filter. This offers the possibility of
pipelining the feed back loop inherent in the HR filters. The digit serial structure is
based on the feed forward of the carry digit, which allows sub digit pipelining to
increase the throughput rate ofthe HR filters.
The implementation of the digital filter was split into its fundamental elements
according to its block diagram. All the elements ofthe filter were designed, simulated
and tested to prove their functionality. Furthermore a 1st order digit-serial HR filter
(n=4, M=32) was composed and simulated to prove that is functioning satisfactorily.
Finally the last should be downloaded onto the FPGA and tested. The FPGA chip,
which was available at the time of this project, was located on a general use board
intended for less complex designs. Due to this fact the 1st order digit-serial filter was
not downloaded, but the 16x16 bit digit-serial multiplier with digit-serial adder and
parallel-in to serial-out register was downloaded instead and tested.
either using VHDL or ECAD programs (Viewlogic).
The application of the digit-serial structures to the design of IIR filters introduces
delay elements in the feed back loop of the HR filter. This offers the possibility of
pipelining the feed back loop inherent in the HR filters. The digit serial structure is
based on the feed forward of the carry digit, which allows sub digit pipelining to
increase the throughput rate ofthe HR filters.
The implementation of the digital filter was split into its fundamental elements
according to its block diagram. All the elements ofthe filter were designed, simulated
and tested to prove their functionality. Furthermore a 1st order digit-serial HR filter
(n=4, M=32) was composed and simulated to prove that is functioning satisfactorily.
Finally the last should be downloaded onto the FPGA and tested. The FPGA chip,
which was available at the time of this project, was located on a general use board
intended for less complex designs. Due to this fact the 1st order digit-serial filter was
not downloaded, but the 16x16 bit digit-serial multiplier with digit-serial adder and
parallel-in to serial-out register was downloaded instead and tested.
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Deliparaschos---1998---BEng-thesis.pdf
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