Design and implementation of a fast digital fuzzy logic controller using FPGA technology
Journal
Journal of Intelligent and Robotic Systems
Date Issued
January 2006
DOI
10.1007/s10846-005-9016-2
Abstract
Fuzzy logic controllers (FLCs) are finding increasing popularity in real industrial
applications, especially when the available system models are inexact or unavailable. This paper
proposes a zero-order Takagi–Sugeno parameterized digital FLC, processing only the active rules
(rules that give a non-null contribution for a given input data set), at high frequency of operation,
without significant increase in hardware complexity. To achieve this goal, an improved method of
designing the fuzzy controller model is proposed that significantly reduces the time required to
process the active rules and effectively increases the input data processing rate. The digital fuzzy
logic controller discussed in this paper achieves an internal core processing speed of at least 200
MHz, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape
membership functions per input and a rule base of up to 49 rules. The proposed architecture was
implemented in a field programmable gate array chip with the use of a very high-speed integratedcircuits
hardware description language and advanced synthesis and place and route tools.
applications, especially when the available system models are inexact or unavailable. This paper
proposes a zero-order Takagi–Sugeno parameterized digital FLC, processing only the active rules
(rules that give a non-null contribution for a given input data set), at high frequency of operation,
without significant increase in hardware complexity. To achieve this goal, an improved method of
designing the fuzzy controller model is proposed that significantly reduces the time required to
process the active rules and effectively increases the input data processing rate. The digital fuzzy
logic controller discussed in this paper achieves an internal core processing speed of at least 200
MHz, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape
membership functions per input and a rule base of up to 49 rules. The proposed architecture was
implemented in a field programmable gate array chip with the use of a very high-speed integratedcircuits
hardware description language and advanced synthesis and place and route tools.