Experimental Investigation and Verification of Traps affecting the performance of 3C-SiC-on-Si Schottky Barrier Diodes
Date Issued
September 1, 2019
DOI
10.1109/ECCE.2019.8912232
Abstract
Monolithic integration of wide bandgap (WBG) devices for power integrated circuits is currently of increased interest. The ability of the cubic phase (3C-) of Silicon Carbide (SiC) to grow heteroepitaxially on Silicon (Si) substrates (3C- SiC-on-Si) is an enabling feature for a cost-effective integration, including the possible integration with Si devices. The isotropic properties of 3C-SiC and the high thermal conductivity also emphasize its importance. In this paper, the authors evaluated the actual 3C-SiC-on-Si material and established a feasible fabrication methodology. In achieving this, non-freestanding lateral Schottky Barrier Diodes (LSBD) have been fabricated and tested. To gain a deep physical insight of the complex phenomena that take place in this material, an advanced Technology Computer Aided Design (TCAD) model was developed which allowed accurate match of measurements with simulations. The model incorporated the device geometry, an accurate representation of the bulk material properties and complex trapping/de-trapping and tunnelling phenomena which appear to affect the device performance. The observed non- uniformities of the Schottky Barrier Height (SBH) were also successfully modelled through the effect of the interfacial traps. The combination of TCAD with fabrication and measurements enabled the identification of the trap profiles and their impact on the electrical performance of this new material, a necessary step towards device designs that take advantage of its properties.
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Experimental_Investigation_and_Verification_of_Traps_affecting_the_performance_of_3C-SiC-on-Si_Schottky_Barrier_Diodes.pdf
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