| Issue Date | Title | Author(s) |
| 1-Oct-2005 | A performance efficient hardware implementation for the encrypted shared storage media standard | Michail, Harris ; Fotopoulou, E. ; Goutis, C. E. ; Milidonis, A. ; Theodoridis, G.; Kakarountas, A. P. |
| Jan-2011 | Performance for cryptography: Ahardware approach | Michail, Harris ; Kakarountas, Athanasios P. |
| Jan-2015 | Pipelined SHA-3 implementations on FPGA: Architecture and performance analysis | Michail, Harris ; Ioannou, Lenos ; Voyiatzis, Artemios G. |
| 1-Dec-2012 | Priority Handling Aggregation Technique (PHAT) for wireless sensor networks | Panagiotou, Christos ; Koubias, Stavros ; Michail, Harris ; Gialelis, John ; Tsitsipis, Dimitris ; Kritikakou, Angeliki S.; Dima, Sofia Maria |
| 2014 | Requirements discovery for smart driver assistive technology through simulation | Gregoriades, Andreas ; Florides, Christos ; Christodoulou, S ; Pampaka, Maria ; Michail, Harris |
| Jun-2009 | An RNS implementation of an Fp elliptic curve point multiplier | Fournaris, Apostolos P. ; Kakarountas, Atharoutas P. ; Michail, Harris ; Stouraitis, Thanos ; Schinianakis, Dimitrios M. |
| Jun-2010 | A robotic system for home security enhancement | Michail, Harris ; Obadan, Samuel ; Gregoriades, Andreas |
| 16-Aug-2010 | A robotic system for home security enhancement | Michael-Grigoriou, Despina ; Gregoriades, Andreas ; Michail, Harris ; Lesta, Vicky Papadopoulou ; Obadan, Samuel |
| Apr-2007 | Server side hashing core exceeding 3 Gbps of throughput | Michail, Harris ; Goutis, Costas E.; Panagiotakopoulos, George A. ; Thanasoulis, Vasilis N. ; Kakarountas, Athanasios P. |
| Jul-2005 | Speeded up and low-powered hardware implementation of the secure hash algorithm through partial unrolling | Michail, Harris ; Kakarountas, Athanasios P. ; Theodoridis, Georgios A. |
| Jul-2013 | A systematic flow for developing totally self-checking architectures for SHA-1 and SHA-2 cryptographic hash families | Athanasiou, George S. ; Theodoridis, G. ; Goutis, Costas E. ; Michail, Harris ; Kasparis, Takis |
| 1-Dec-2006 | Temporal and system level modifications for high speed VLSI implementations of cryptographic core | Thanasoulis, V. N. ; Milidonis, A. S. ; Kakarountas, A. P. ; Goutis, C. E. ; Panagiotakopoulos, G. A. ; Michail, Harris |
| Dec-2006 | Temporal and system level modifications for high speed VLSI implementations of cryptographic core | Michail, Harris ; Kakarountas, Athanasios P. ; Milidonis, Athanasios S. |
| Aug-2007 | Throughput optimization of the cipher message authentication code | Selimis, G. ; Michail, Harris ; Kakarountas, A. P. ; Goutis, C. E. |
| Oct-2009 | A top-down design methodology for ultrahigh-performance hashing cores | Michail, Harris ; Kakarountas, Athanasios P. ; Milidonis, Athanasios S. ; Goutis, Costas E. |
| Jul-2010 | Ultra high speed SHA-256 hashing cryptographic module for IPSEC hardware/software codesign | Michail, Harris ; Athanasiou, George S. ; Kritikakou, Angeliki S. |
| 1-Dec-2010 | Ultra high speed SHA-256 hashing cryptographic module for IPSEC hardware/software codesign | Michail, Harris ; Athanasiou, George S. ; Kritikakou, Angeliki S. ; Goutis, Costas E. ; Gregoriades, Andreas ; Papadopoulou, Vicky |
| 1-Dec-2005 | VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption | Lazarou, N. ; Michail, Harris ; Koufopavlou, O. ; Selimis, G. |
| Dec-2005 | VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption | Michail, Harris ; Selimis, George N. ; Koufopavlou, Odysseas G. |