Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/13971
Title: Temporal and system level modifications for high speed VLSI implementations of cryptographic core
Authors: Thanasoulis, V. N. 
Milidonis, A. S. 
Kakarountas, A. P. 
Goutis, C. E. 
Panagiotakopoulos, G. A. 
Michail, Harris 
Major Field of Science: Engineering and Technology
Field Category: Electrical Engineering - Electronic Engineering - Information Engineering
Issue Date: 1-Dec-2006
Source: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Conference: IEEE International Conference on Electronics, Circuits, and Systems 
Abstract: Hash functions are forming a special family of cryptographic algorithms, which are applied wherever message integrity and authentication issues are critical. As time passes it seems that all applications call for higher throughput due to their rapid acceptance by the market. In this work a new technique is presented for increasing frequency and throughput of the currently most used hash function, which is SHA-1. This technique involves the application of spatial and temporal pre-computation. Comparing to conventional pipelined implementations of hash functions the proposed technique leads to an implementation with more than 75% higher throughput © 2006 IEEE.
URI: https://hdl.handle.net/20.500.14279/13971
ISBN: 1424403952
DOI: 10.1109/ICECS.2006.379651
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια /Conference papers or poster or presentation

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