Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/9699
DC FieldValueLanguage
dc.contributor.authorAthanasiou, George S.-
dc.contributor.authorMichail, Harris-
dc.contributor.authorTheodoridis, George-
dc.contributor.authorGoutis, Costas E.-
dc.date.accessioned2017-02-15T14:22:09Z-
dc.date.available2017-02-15T14:22:09Z-
dc.date.issued2014-03-
dc.identifier.citationIET Computers and Digital Techniques, vol. 8, no. 2, 2014, pp. 70-82en_US
dc.identifier.issn17518601-
dc.identifier.urihttps://hdl.handle.net/20.500.14279/9699-
dc.description.abstractIn this study, novel pipelined architectures, optimised in terms of throughput and throughput/area factors, for the SHA-512 cryptographic hash function, are proposed. To achieve this, algorithmic- and circuit-level optimisation techniques such as loop unrolling, re-timing, temporal pre-computation, resource re-ordering and pipeline are applied. All the techniques, except pipeline are applied in the function's transformation round. The pipeline was applied through the development of all the alternative pipelined architectures and implementation in several Xilinx FPGA families and they are evaluated in terms of frequency, area, throughput and throughput/area factors. Compared to the initial un-optimised implementation of SHA-512 function, the introduced five-stage pipelined architecture improves the both the throughput and throughput/area factors by 123 and 61.5%, respectively. Furthermore, the proposed five-stage pipelined architecture outperforms the existing ones both in throughput (3.4× up to 16.9×) and throughput/area (19.5% up to 6.9×) factors.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.relation.ispartofIET Computers and Digital Techniquesen_US
dc.rights© The Institution of Engineering and Technologyen_US
dc.subjectHash functionsen_US
dc.subjectPipeline processing systemsen_US
dc.subjectPipelinesen_US
dc.subjectTiming circuitsen_US
dc.titleOptimising the SHA-512 cryptographic hash function on FPGAsen_US
dc.typeArticleen_US
dc.collaborationCyprus University of Technologyen_US
dc.collaborationUniversity of Patrasen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.journalsSubscriptionen_US
dc.countryCyprusen_US
dc.countryGreeceen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1049/iet-cdt.2013.0010en_US
dc.relation.issue2en_US
dc.relation.volume8en_US
cut.common.academicyear2013-2014en_US
dc.identifier.spage70en_US
dc.identifier.epage82en_US
item.fulltextNo Fulltext-
item.languageiso639-1en-
item.grantfulltextnone-
item.openairecristypehttp://purl.org/coar/resource_type/c_6501-
item.cerifentitytypePublications-
item.openairetypearticle-
crisitem.journal.journalissn1751-861X-
crisitem.journal.publisherThe Institution of Engineering and Technology-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-8299-8737-
crisitem.author.parentorgFaculty of Engineering and Technology-
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