Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/9570
DC FieldValueLanguage
dc.contributor.authorMichail, Harris-
dc.contributor.authorIoannou, Lenos-
dc.contributor.authorVoyiatzis, Artemios G.-
dc.contributor.otherΙωάννου, Λένος-
dc.date.accessioned2017-02-09T12:31:00Z-
dc.date.available2017-02-09T12:31:00Z-
dc.date.issued2015-01-
dc.identifier.citation(2015) ACM International Conference Proceeding Series, 2015-January, pp. 13-18; 2nd Workshop on Cryptography and Security in Computing Systems, CS2 2015, Amsterdam, Netherlands, 19 January 2015 throughen_US
dc.identifier.isbn978-145033187-6-
dc.description.abstract.Efficient and high-throughput designs of hash functions will be in great demand in the next few years, given that every IPv6 data packet is expected to be handled with some kind of security features. In this paper, pipelined implementations of the new SHA- 3 hash standard on FPGAs are presented and compared aiming to map the design space and the choice of the number of pipeline stages. The proposed designs support all the four SHA-3 modes of operation. They also support processing of multiple messages each comprising multiple blocks. Designs for up to a four-stage pipeline are presented for three generations of FPGAs and the performance of the implementations is analyzed and compared in terms of the throughput/area metric. Several pipeline designs are explored in order to determine the one that achieves the best throughput/area performance. The results indicate that the FPGA technology characteristics must also be considered when choosing an efficient pipeline depth. Our designs perform better compared to the existing literature due to the extended optimization effort on the synthesis tool and the efficient design of multiblock message processing.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.rights© 2014 Association for Computing Machinery (ACM)en_US
dc.subjectCryptographyen_US
dc.subjectFPGAen_US
dc.subjectHash functionen_US
dc.subjectPipelineen_US
dc.subjectSecurityen_US
dc.titlePipelined SHA-3 implementations on FPGA: Architecture and performance analysisen_US
dc.typeConference Papersen_US
dc.collaborationCyprus University of Technologyen_US
dc.collaborationIndustrial Systems Institute/RC Athenaen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.countryCyprusen_US
dc.countryGreeceen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.relation.conferenceWorkshop on Cryptography and Security in Computing Systemsen_US
dc.identifier.doi10.1145/2694805.2694808en_US
cut.common.academicyear2014-2015en_US
item.cerifentitytypePublications-
item.languageiso639-1en-
item.fulltextNo Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_c94f-
item.openairetypeconferenceObject-
item.grantfulltextnone-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-8299-8737-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
Appears in Collections:Δημοσιεύσεις σε συνέδρια /Conference papers or poster or presentation
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