On the development of totally self-checking hardware design for the SHA-1 hash function
Date Issued
July 2012
DOI
10.5220/0004059302700275
Abstract
Hash functions are among the major blocks of modern security schemes, used in many applications to provide authentication services. To meet the applications' real-time constraints, they are implemented in hardware offering high-performance and increased security solutions. However, faults occurred during their operation result in the collapse of the authentication procedure, especially when they are used in securitycritical applications such as military or space ones. In this paper, a Totally Self-Checking (TSC) design is introduced for the currently most-used hash function, namely the SHA-1. A detailed description concerning the TSC development of the data- and control-path is provided. To the best of authors' knowledge, it is the first time that a TSC hashing core is presented. The proposed design has been implemented in 0.18mm CMOS technology and experiments on fault caverage, performance, and area have been performed. It achieves 100% coverage in the case of odd erroneous bits. The same coverage is also achieved for even erroneous bits, if they are appropriately spread. Compared to the corresponding Duplicated-with-Checking (DWC) design, the proposed one is more area-efficient by almost 15% keeping the same frequency.