On the 3C-SiC/SiO2n-MOS interface and the creation of a calibrated model for the Electrons' Inversion Layer Mobility covering a wide range of operating temperatures and applied gate voltage
Date Issued
January 1, 2022
DOI
10.1109/WiPDAEurope55971.2022.9936319
Abstract
Cubic (3C-) silicon carbide (SiC) metal oxide semiconductor (MOS) devices have the potential to achieve superior performance and reliability. The effective channel mobility can be significantly higher compared to other SiC polytypes due to the smaller concentration of active SiC/SiO2 interface traps and the gate leakage current can be smaller than other SiC polytypes and silicon (Si) because of the more favourable conduction band offset between 3C-SiC and silicon dioxide (SiO2). This work examines the 3C-SiC/SiO2 n-MOS interface and makes use of three independent sets of experimental data to derive and validate a comprehensive model of the inversion layer mobility in 3C-SiC n-MOS structures. The model derived in this work can be used by technology computer aided design (TCAD) tools and can predict the channel mobility with reasonable accuracy for gate voltages ranging 0V - 20V, and for temperatures ranging 300K - 473K. The ability to reproduce correctly the physical phenomena affecting the 3C-SiC/Si02 n-MOS channel mobility in TCAD through an appropriately parameterised model is imperative for the design and optimization of MOS devices like MOSFETs and IGBTs and the further development of 3C-SiC device technology.
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On_the_3C-SiC_SiO2_n-MOS_interface_and_the_creation_of_a_calibrated_model_for_the_Electrons_Inversion_Layer_Mobility_covering_a_wide_range_of_operating_.pdf
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