Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/2394
Title: A decoupled architecture of processors with scratch-pad memory hierarchy
Authors: Michail, Harris 
Milidonis, Athanasios S. 
Alachiotis, Nikolaos 
metadata.dc.contributor.other: Μιχαήλ, Χάρης
Major Field of Science: Engineering and Technology
Field Category: Electrical Engineering - Electronic Engineering - Information Engineering
Keywords: Data processing;Software architecture;Synchronization;Application software
Issue Date: Apr-2007
Source: (2007) Proceedings -Design, Automation and Test in Europe, DATE, art. no. 4211866, pp. 612-617; Design, Automation and Test in Europe Conference and Exhibition, 2007, Nice, France
Conference: Design, Automation and Test in Europe Conference and Exhibition 
Abstract: We present a decoupled architecture of processors with a memory hierarchy of only scratch-pad memories, and a main memory. The decoupled architecture also exploits the parallelism between address computation and processing the application data. The application code is split in two programs the first for computing the addresses of the data in the memory hierarchy and the second for processing the application data. The first program is executed by one of the decoupled processors called Access which uses compiler methods for placing data in the memory hierarchy. In parallel, the second program is executed by the other processor called Execute. The synchronization of the memory hierarchy and the Execute processor is achieved through simple handshake protocol. The Access processor requires strong communication with the memory hierarchy which strongly differentiates it from traditional uniprocessors. The architecture is compared in performance with the MIPS IV architecture of SimpleScalar and with the existing decoupled architectures showing its higher normalized performance. Experimental results show that the performance is increased up to 3.7 times. Compared with MIPS IV the proposed architecture achieves the above performance with insignificant overheads in terms of area
ISSN: 1530-1591
DOI: 10.1109/DATE.2007.364661
Rights: © 2007 EDAA
Type: Conference Papers
Affiliation: University of Patras 
Affiliation : University of Patras 
Funding: European Design and Automation Association,The EDA Consortium,The IEEE Computer Society TTTC,IEEE Council on Electronic Design Automation, CEDA,ECSI,et al
Publication Type: Peer Reviewed
Appears in Collections:Δημοσιεύσεις σε συνέδρια /Conference papers or poster or presentation

CORE Recommender
Show full item record

SCOPUSTM   
Citations 20

1
checked on Nov 6, 2023

Page view(s) 20

443
Last Week
0
Last month
4
checked on Dec 23, 2024

Google ScholarTM

Check

Altmetric


Items in KTISIS are protected by copyright, with all rights reserved, unless otherwise indicated.