Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/1717
DC FieldValueLanguage
dc.contributor.authorMichail, Harris-
dc.contributor.authorSelimis, George N.-
dc.contributor.authorFournaris, Apostolos P.-
dc.date.accessioned2013-02-21T13:33:44Zen
dc.date.accessioned2013-05-17T05:22:39Z-
dc.date.accessioned2015-12-02T10:00:07Z-
dc.date.available2013-02-21T13:33:44Zen
dc.date.available2013-05-17T05:22:39Z-
dc.date.available2015-12-02T10:00:07Z-
dc.date.issued2009-02-
dc.identifier.citationIntegration, 2009, vol. 42, no. 2, pp. 217-226en_US
dc.identifier.issn01679260-
dc.identifier.urihttps://hdl.handle.net/20.500.14279/1717-
dc.description.abstractHigh throughput is a crucial factor in bit-serial GF(2m) fields multiplication for a variety of different applications including cryptography, error coding detection and computer algebra. The throughput of a multiplier is dependent on the required number of clock cycles to reach a result and its critical path delay. However, most bit-serial GF(2m) multipliers do not manage to reduce the required number of clock cycles below the threshold of m clock cycles without increasing dramatically their critical path delay. This increase is more evident if a multiplier is designed to be versatile. In this article, a new versatile bit-serial MSB multiplier for GF(2m) fields is proposed that achieves a 50% increase on average in throughput when compared to other designs, with a very small increase in its critical path delay. This is achieved by an average 33.4% reduction in the required number of clock cycles below m. The proposed design can handle arbitrary bit-lengths upper bounded by m and is suitable for applications where the field order may vary.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.relation.ispartofIntegrationen_US
dc.rights© Elsevieren_US
dc.subjectCryptographyen_US
dc.subjectHardwareen_US
dc.subjectMultiplicationen_US
dc.titleImproved throughput bit-serial multiplier for GF(2m) fieldsen_US
dc.typeArticleen_US
dc.affiliationUniversity of Patrasen
dc.collaborationUniversity of Patrasen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.journalsSubscriptionen_US
dc.countryGreeceen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1016/j.vlsi.2008.07.003en_US
dc.dept.handle123456789/54en
dc.relation.issue2en_US
dc.relation.volume42en_US
cut.common.academicyear2008-2009en_US
dc.identifier.spage217en_US
dc.identifier.epage226en_US
item.grantfulltextnone-
item.openairecristypehttp://purl.org/coar/resource_type/c_6501-
item.fulltextNo Fulltext-
item.languageiso639-1en-
item.cerifentitytypePublications-
item.openairetypearticle-
crisitem.journal.journalissn0167-9260-
crisitem.journal.publisherElsevier-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-8299-8737-
crisitem.author.parentorgFaculty of Engineering and Technology-
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