Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/1602
DC FieldValueLanguage
dc.contributor.authorMichail, Harris-
dc.contributor.authorKakarountas, Athanasios P.-
dc.contributor.authorMilidonis, Athanasios S.-
dc.contributor.authorGoutis, Costas E.-
dc.date.accessioned2013-02-21T13:41:35Zen
dc.date.accessioned2013-05-17T05:22:39Z-
dc.date.accessioned2015-12-02T10:01:25Z-
dc.date.available2013-02-21T13:41:35Zen
dc.date.available2013-05-17T05:22:39Z-
dc.date.available2015-12-02T10:01:25Z-
dc.date.issued2009-10-
dc.identifier.citationIEEE Transactions on Dependable and Secure Computing, 2009, vol. 6, no. 4, pp. 255-268en_US
dc.identifier.issn19410018-
dc.identifier.urihttps://hdl.handle.net/20.500.14279/1602-
dc.description.abstractMany cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of cryptographic algorithms. Applications that use these security schemes are becoming very popular as time goes by and this means that some of these applications call for higher throughput either due to their rapid acceptance by the market or due to their nature. In this work, a new methodology is presented for achieving high operating frequency and throughput for the implementations of all widely usedand those expected to be used in the near futurehash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, SHA-512, and so forth. In the proposed methodology, five different techniques have been developed and combined with the finest way so as to achieve the maximum performance. Compared to conventional pipelined implementations of hash functions (in FPGAs), the proposed methodology can lead even to a 160 percent throughput increase.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.relation.ispartofIEEE Transactions on Dependable and Secure Computingen_US
dc.rights© IEEEen_US
dc.subjectIntegrityen_US
dc.subjectAuthenticationen_US
dc.subjectCryptographyen_US
dc.subjectHardwareen_US
dc.titleA top-down design methodology for ultrahigh-performance hashing coresen_US
dc.typeArticleen_US
dc.affiliationUniversity of Patrasen
dc.collaborationUniversity of Patrasen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.journalsSubscriptionen_US
dc.countryGreeceen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1109/TDSC.2008.15en_US
dc.dept.handle123456789/54en
dc.relation.issue4en_US
dc.relation.volume6en_US
cut.common.academicyear2009-2010en_US
dc.identifier.spage255en_US
dc.identifier.epage268en_US
item.fulltextNo Fulltext-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.openairecristypehttp://purl.org/coar/resource_type/c_6501-
item.openairetypearticle-
item.languageiso639-1en-
crisitem.journal.journalissn1941-0018-
crisitem.journal.publisherIEEE-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-8299-8737-
crisitem.author.parentorgFaculty of Engineering and Technology-
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