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https://hdl.handle.net/20.500.14279/13951| Title: | Holistic methodology for designing ultra high-speed SHA-1 hashing cryptographic module in hardware | Authors: | Michail, Harris Goutis, C. |
Major Field of Science: | Engineering and Technology | Field Category: | Electrical Engineering - Electronic Engineering - Information Engineering | Keywords: | Hash functions;Field programmable gate arrays (FPGA);Cryptographic hash | Issue Date: | 1-Dec-2008 | Source: | (2008) IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, art. no. 4760668 | Conference: | IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC | Abstract: | Nowadays security is a critical issue as long as electronic transactions are concerned. Moreover taking into consideration the rapid growth of e-commerce and the future needs, it is essential to achieve higher throughput rates for the incorporated security schemes. The most common components in such security schemes are a cipher block and a hash function, with the second one being hard to compete with the throughput achieved by cipher blocks. In this paper a top-down methodology is presented which manages to increase throughput of SHA-1 hash function hardware design about 160% comparing to conventional implementations with a minor area penalty. © 2008 IEEE. | ISBN: | 978-142442540-2 | DOI: | 10.1109/EDSSC.2008.4760668 | Rights: | © 2008 IEEE | Type: | Conference Papers | Affiliation : | University of Patras |
| Appears in Collections: | Δημοσιεύσεις σε συνέδρια /Conference papers or poster or presentation |
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