High-throughput hardware architectures of the JH round-three SHA-3 candidate: An FPGA design and implementation approach

Abstract

Hash functions are exploited by many cryptographic primitives that are incorporated in crucial cryptographic schemes and commercial security protocols. Nowadays, there is an active international competition, launched by the National Institute of Standards and Technology (NIST), for establishing the new hash standard, SHA-3. One of the semi-finalists is the JH algorithm. In this paper, two high throughput hardware architectures of the complete JH algorithm are presented. The difference between them is the existence of 3 pipeline stages at the second one. They both are designed to support all the possible versions of the algorithm and are implemented in Xilinx Virtex-4, Virtex-5, and Virtex-6 FPGAs. Based on the experimental results, the proposed architectures outperform the existing ones in terms of Throughput/Area factor, regarding all FPGA platforms and JH algorithm's versions.