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Πεδίο DCΤιμήΓλώσσα
dc.contributor.authorEisley, Noel A.-
dc.contributor.authorWang, Hangsheng-
dc.contributor.authorLi, Bin-
dc.contributor.authorPeh, Lishiuan-
dc.contributor.authorSoteriou, Vassos-
dc.contributor.otherΣωτηρίου, Βάσος-
dc.date.accessioned2009-12-22T10:54:18Zen
dc.date.accessioned2013-05-17T05:23:09Z-
dc.date.accessioned2015-12-02T10:19:21Z-
dc.date.available2009-12-22T10:54:18Zen
dc.date.available2013-05-17T05:23:09Z-
dc.date.available2015-12-02T10:19:21Z-
dc.date.issued2007-07-
dc.identifier.citationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007. vol. 15, no. 8, pp. 855-868en_US
dc.identifier.issn10638210-
dc.identifier.urihttps://hdl.handle.net/20.500.14279/1328-
dc.description.abstractTechnology trends are driving parallel on-chip architectures in the form of multiprocessor systems-on-a-chip (MPSoCs) and chip multiprocessors (CMPs). In these systems, the increasing on-chip communication demand among the computation elements necessitates the use of scalable, high-bandwidth network-on-chip (NoC) fabrics instead of dedicated interconnects and shared buses. As transistor feature sizes are further miniaturized, more complicated NoC architectures become feasible that can support more demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design-space to predict the interconnect fabric(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris, a system-level roadmapping toolchain for on-chip interconnection networks that helps designers predict the most suitable interconnection network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that the system will run. Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While Polaris's toolchain is extensible so new traffic, network designs, and technology processes can be added, the current version already incorporates 7872 NoC design points. Polaris is rapid, efficiently iterating over thousands of NoC design points, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.rights© IEEEen_US
dc.titlePolaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networksen_US
dc.typeArticleen_US
dc.affiliationPrinceton Universityen
dc.collaborationPrinceton Universityen_US
dc.subject.categoryComputer and Information Sciencesen_US
dc.journalsSubscriptionen_US
dc.countryCyprusen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1109/TVLSI.2007.900725en_US
dc.dept.handle123456789/54en
dc.relation.issue8en_US
dc.relation.volume15en_US
cut.common.academicyear2006-2007en_US
dc.identifier.spage855en_US
dc.identifier.epage868en_US
item.fulltextNo Fulltext-
item.languageiso639-1en-
item.grantfulltextnone-
item.openairecristypehttp://purl.org/coar/resource_type/c_6501-
item.cerifentitytypePublications-
item.openairetypearticle-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-2818-0459-
crisitem.author.parentorgFaculty of Engineering and Technology-
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