Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis
Date Issued
September 12, 2017
DOI
10.1109/ETFA.2017.8247736
Abstract
This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.