Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/4264
DC FieldValueLanguage
dc.contributor.authorVitkovskiy, Arseniy-
dc.contributor.authorNicopoulos, Chrysostomos-
dc.contributor.authorSoteriou, Vassos-
dc.contributor.otherΣωτηρίου, Βάσος-
dc.date.accessioned2013-02-18T09:00:18Zen
dc.date.accessioned2013-05-17T10:38:32Z-
dc.date.accessioned2015-12-09T12:04:14Z-
dc.date.available2013-02-18T09:00:18Zen
dc.date.available2013-05-17T10:38:32Z-
dc.date.available2015-12-09T12:04:14Z-
dc.date.issued2010-
dc.identifier.citation2010 IEEE International conference on computer design (ICCD), pp. 447-454en_US
dc.identifier.isbn978-1-4244-8935-0-
dc.description.abstractSilicon technology scaling is continuously enabling denser integration capabilities. However, this comes at the expense of higher variability and susceptibility to wear-out. With an escalating number of on-chip components expected to be defective in near-future chips, modern parallel systems, such as Chip Multi-Processors (CMP), become especially vulnerable to these faults. Just a single link failure in the underlying Network on-Chip (NoC) may cause inter-tile communication to halt and even deadlock, rendering the chip useless. While fault-tolerant routing schemes do exist, they can only handle a finite number of link faults. In this paper, we address permanent wire failures which can occur in on-chip parallel links at manufacture-time or while in operation. Instead of marking the entire link as faulty, we present a methodology where the Partially Faulty Link (PFL) can still be used to transfer data between NoC routers, thus maintaining network connectivity, extending the yield and lifetime of the chip, and allowing for graceful performance degradation. To achieve this, we devise architectural augmentations both to the router and link micro-architectures, along with link fault detection, diagnosis, and re-configuration at the level of wire granularity. Statistical link-level fault models present the usability of PFLs, while relevant load-balancing routing algorithms and low-cost re-transmission mechanisms are also presented and coupled to the proposed architecture. Hardware synthesis demonstrates the feasibility of the proposed extensions to the base NoC architecture. Results obtained from full-system simulations show that high-performance NoCs are realizable in the presence of PFLsen_US
dc.language.isoenen_US
dc.rights© Copyright 2010 IEEEen_US
dc.subjectComputer scienceen_US
dc.subjectComputer architectureen_US
dc.subjectHardwareen_US
dc.subjectNetworks on a chipen_US
dc.subjectFault tolerant computingen_US
dc.subjectMicroprocessorsen_US
dc.subjectComputer network architecturesen_US
dc.subjectRouters (Computer networks)en_US
dc.titleA fine-grained link-level fault-tolerant mechanism for networks-on-chipen_US
dc.typeConference Papersen_US
dc.collaborationCyprus University of Technologyen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.reviewpeer reviewed-
dc.countryCyprusen_US
dc.subject.fieldEngineering and Technologyen_US
dc.relation.conferenceIEEE International Conference on Computer Design, ICCDen_US
dc.identifier.doi10.1109/ICCD.2010.5647663en_US
dc.dept.handle123456789/134en
cut.common.academicyear2010-2011en_US
item.openairecristypehttp://purl.org/coar/resource_type/c_c94f-
item.openairetypeconferenceObject-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.languageiso639-1en-
item.fulltextNo Fulltext-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-2818-0459-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
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