Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.14279/4260
DC FieldValueLanguage
dc.contributor.authorEvripidou, Marios-
dc.contributor.authorNicopoulos, Chrysostomos-
dc.contributor.authorSoteriou, Vassos-
dc.contributor.otherΣωτηρίου, Βάσος-
dc.contributor.otherΕυριπίδου, Μάριος-
dc.contributor.otherΝικόπουλος, Χρυσόστομος-
dc.date.accessioned2013-02-15T09:10:06Zen
dc.date.accessioned2013-05-17T10:38:30Z-
dc.date.accessioned2015-12-09T12:04:10Z-
dc.date.available2013-02-15T09:10:06Zen
dc.date.available2013-05-17T10:38:30Z-
dc.date.available2015-12-09T12:04:10Z-
dc.date.issued2012-08-
dc.identifier.citation2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 19-21 August 2012, pp. 21-26en_US
dc.identifier.isbn978-1-4673-2234-8-
dc.identifier.urihttps://hdl.handle.net/20.500.14279/4260-
dc.description.abstractThe Network-on-Chip (NoC) router buffers are instrumental in the overall operation of Chip Multi-Processors (CMP), because they facilitate the creation of Virtual Channels (VC). Both the NoC routing algorithm and the CMP's cache coherence protocol rely on the presence of VCs within the NoC for correct functionality. In this article, we introduce a novel concept that completely decouples the number of supported VCs from the number of VC buffers physically present in the design. Virtual Channel Renaming enables the virtualization of existing virtual channels, in order to support an arbitrarily large number of VCs. Hence, the CMP can (a) withstand the presence of faulty VCs, and (b) accommodate routing algorithms and/or coherence protocols with disparate VC requirements. The proposed VC Renamer architecture incurs minimal hardware overhead to existing NoC designs and is shown to exhibit excellent performance without affecting the router's critical pathen_US
dc.language.isoenen_US
dc.rights© Copyright 2012 IEEEen_US
dc.subjectComputer architectureen_US
dc.subjectRouters (Computer networks)en_US
dc.subjectNetworks on a chipen_US
dc.subjectHardwareen_US
dc.titleVirtualizing virtual channels for increased network-on-chip robustness and upgradeabilityen_US
dc.typeBook Chapteren_US
dc.collaborationUniversity of Cyprusen_US
dc.collaborationCyprus University of Technologyen_US
dc.subject.categoryComputer and Information Sciencesen_US
dc.reviewpeer reviewed-
dc.countryCyprusen_US
dc.subject.fieldEngineering and Technologyen_US
dc.relation.conferenceIEEE Computer Society Annual Symposium on VLSI (ISVLSI)en_US
dc.identifier.doi10.1109/ISVLSI.2012.44en_US
dc.dept.handle123456789/134en
cut.common.academicyear2012-2013en_US
item.fulltextNo Fulltext-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.openairecristypehttp://purl.org/coar/resource_type/c_3248-
item.openairetypebookPart-
item.languageiso639-1en-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-2818-0459-
crisitem.author.parentorgFaculty of Engineering and Technology-
Appears in Collections:Κεφάλαια βιβλίων/Book chapters
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