Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/9849
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dc.contributor.authorMichail, Harris-
dc.contributor.authorAthanasiou, George S.-
dc.contributor.authorTheodoridis, George-
dc.contributor.authorGoutis, Costas E.-
dc.contributor.otherΜιχαήλ, Χάρης-
dc.date.accessioned2017-02-23T10:59:33Z-
dc.date.available2017-02-23T10:59:33Z-
dc.date.issued2014-09-
dc.identifier.citationIntegration, the VLSI Journal, vol. 47, no. 4, September 2014, pp. 387-407en_US
dc.identifier.issn0167-9260-
dc.description.abstractIn this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.publisherElsevier Ltden_US
dc.relation.ispartofIntegration, the VLSI Journalen_US
dc.rights© 2014 WILEYen_US
dc.subjectAuthenticationen_US
dc.subjectFPGAen_US
dc.subjectHashen_US
dc.subjectMulti-modeen_US
dc.titleOn the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAsen_US
dc.typeArticleen_US
dc.doihttp://dx.doi.org/10.1016/j.vlsi.2014.02.004en_US
dc.collaborationCyprus University of Technologyen_US
dc.collaborationAntcor - Advanced Network Technologies S.A.en_US
dc.collaborationUniversity of Patrasen_US
dc.subject.categoryComputer and Information Sciencesen_US
dc.journalsSubscription Journalen_US
dc.countryCyprusen_US
dc.countryGreeceen_US
dc.subject.fieldNatural Sciencesen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1016/j.vlsi.2014.02.004en_US
cut.common.academicyear2014-2015en_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.languageiso639-1other-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
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