Please use this identifier to cite or link to this item:
|Title:||On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs||Authors:||Michail, Harris
Athanasiou, George S.
Goutis, Costas E.
|Keywords:||Authentication;FPGA;Hash;Multi-mode||Category:||Computer and Information Sciences||Field:||Natural Sciences||Issue Date:||Sep-2014||Publisher:||Elsevier Ltd||Source:||Integration, the VLSI Journal, vol. 47, no. 4, September 2014, pp. 387-407||DOI:||http://dx.doi.org/10.1016/j.vlsi.2014.02.004||Journal:||Integration, the VLSI Journal||Abstract:||In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.||ISSN:||0167-9260||DOI:||10.1016/j.vlsi.2014.02.004||Rights:||© 2014 WILEY||Type:||Article|
|Appears in Collections:||Άρθρα/Articles|
Show full item record
WEB OF SCIENCETM
checked on Aug 11, 2019
checked on Aug 19, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.