Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/9843
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dc.contributor.authorAthanasiou, George S.-
dc.contributor.authorTheodoridis, G.-
dc.contributor.authorGoutis, Costas E.-
dc.contributor.authorMichail, Harris-
dc.contributor.authorKasparis, Takis-
dc.contributor.otherΜιχαήλ, Χάρης-
dc.contributor.otherΚασπαρής, Τάκης-
dc.date.accessioned2017-02-23T10:48:25Z-
dc.date.available2017-02-23T10:48:25Z-
dc.date.issued2013-07-
dc.identifier.citationJournal of Circuits, Systems and Computers, 2013, vol. 22, no. 6en_US
dc.identifier.issn0218-1266-
dc.description.abstractHash functions are among the crucial modules of modern hardware cryptographic systems. These systems frequently operate in harsh and noisy environments where permanent and/or transient faults are often causing erroneous authentication results and collapsing of the whole authentication procedure. Hence, their on-time detection is an urgent feature. In this paper, a systematic development flow towards totally self-checking (TSC) architectures of the most widely-used cryptographic hash families, SHA-1 and SHA-2, is proposed. Novel methods and techniques are introduced to determine the appropriate concurrent error detection scheme at high level avoiding gate-level implementations and comparisons. The resulted TSC architectures achieve 100% fault detection of odd erroneous bits, while, depending on the designer's choice, even number of erroneous bits can also be detected. Two representative functions of the above families, namely the SHA-1 and SHA-256, are used as case studies. For each of them, two TSC architectures (one un-optimized and one optimized for throughput) were developed via the proposed flow and implemented in TSMC 0.18 μm CMOS technology. The produced architectures are more efficient in terms of throughput/area than the corresponding duplicated-with-checking ones by 19.5% and 23.8% regarding the un-optimized TSC SHA-1 and SHA-256 and by 20.2% and 24.6% regarding the optimized ones.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.publisherWorld Scientific Publishing Co. Pte Ltden_US
dc.relation.ispartofJournal of Circuits, Systems and Computersen_US
dc.rights© 2013 World Scientific Publishing Company.en_US
dc.subjectCryptographyen_US
dc.subjectError detectionen_US
dc.subjectHash functionsen_US
dc.subjectSHA-1en_US
dc.subjectSHA-2en_US
dc.subjectTotally self-checkingen_US
dc.titleA systematic flow for developing totally self-checking architectures for SHA-1 and SHA-2 cryptographic hash familiesen_US
dc.typeArticleen_US
dc.collaborationUniversity of Patrasen_US
dc.collaborationCyprus University of Technologyen_US
dc.subject.categoryComputer and Information Sciencesen_US
dc.journalsSubscription Journalen_US
dc.countryGreeceen_US
dc.countryCyprusen_US
dc.subject.fieldNatural Sciencesen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1142/S0218126613500497en_US
cut.common.academicyear2012-2013en_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.languageiso639-1other-
crisitem.journal.journalissn1793-6454-
crisitem.journal.publisherWorld Scientific Publishing Co-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
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