Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/9815
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dc.contributor.authorVitkovskiy, Arseniy-
dc.contributor.authorSoteriou, Vassos-
dc.contributor.authorNicopoulos, Chrysostomos-
dc.contributor.otherΣωτηρίου, Βάσος-
dc.date.accessioned2017-02-20T12:40:38Z-
dc.date.available2017-02-20T12:40:38Z-
dc.date.issued2013-07-31-
dc.identifier.citationIET Computers and Digital Techniques, 2013, vol. 7, no. 2, pp. 93-103en_US
dc.identifier.issn1751-8601-
dc.description.abstractDownscaled complementary metal-oxide semiconductor (CMOS) technology feature sizes have enabled massive transistor integration densities. Multi-core chips with billions of transistors are now a reality. However, this rapid increase in on-chip resources has come at the expense of higher susceptibility to defects and wear-out. The inter-router communication links of networks-on-chips (NoCs) are composed of metal wires that are especially vulnerable to catastrophic physical effects such as those of electro-migration, which can even cause link disconnects. To address this hazard, fault-tolerant (FT) routing algorithms sustain on-chip communication by re-routing messages around faulty links, or regions. This work presents a new FT routing scheme that employs a localised re-routing approach. Packets are de-toured around faulty links/regions based on purely local and distributed decisions, and without any global link state knowledge. The algorithm, which is proven to be deadlock-and livelock-free, also handles dynamically occurring faults. Detailed evaluation with synthetic traffic patterns and real applications within a full-system simulation environment demonstrate the efficacy of the new scheme with up to 12% of NoC links being faulty. Synthesis results also prove the feasibility of the proposed protocol at modest hardware and power consumption overheads of only over 5 and 2.5%, respectively.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.publisherInstitution of Engineering and Technologyen_US
dc.relation.ispartofIET Computers and Digital Techniquesen_US
dc.rights© The Institution of Engineering and Technology 2013.en_US
dc.subjectComplementary metal oxide semiconductorsen_US
dc.subjectDistributed decisionen_US
dc.subjectFault-tolerant routing algorithmen_US
dc.subjectFull-system simulationen_US
dc.subjectIntegration densityen_US
dc.subjectNetworks on chipsen_US
dc.subjectOn chip communicationen_US
dc.subjectReal applicationsen_US
dc.titleDynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring pathsen_US
dc.typeArticleen_US
dc.collaborationCyprus University of Technologyen_US
dc.collaborationUniversity of Cyprusen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.journalsSubscription Journalen_US
dc.countryCyprusen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1049/iet-cdt.2012.0054en_US
cut.common.academicyear2012-2013en_US
item.openairetypearticle-
item.grantfulltextnone-
item.openairecristypehttp://purl.org/coar/resource_type/c_6501-
item.cerifentitytypePublications-
item.languageiso639-1en-
item.fulltextNo Fulltext-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-2818-0459-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.journal.journalissn1751-861X-
crisitem.journal.publisherThe Institution of Engineering and Technology-
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