Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/9771
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dc.contributor.authorKim, Hyungjun-
dc.contributor.authorVitkovskiy, Arseniy-
dc.contributor.authorGratz, Paul V.-
dc.contributor.authorSoteriou, Vassos-
dc.contributor.otherΣωτηρίου, Βάσος-
dc.date.accessioned2017-02-17T11:57:43Z-
dc.date.available2017-02-17T11:57:43Z-
dc.date.issued2013-12-01-
dc.identifier.citation46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013, United Statesen_US
dc.identifier.isbn978-145032638-4-
dc.description.abstractMoore's Law scaling is continuing to yield even higher transistor density with each succeeding process generation, leading to today's multi-core Chip Multi-Processors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep sub-micron CMOS process technology is marred by increasing susceptibility to wearout. Prolonged operational stress gives rise to accelerated wearout and failure, due to several physical failure mechanisms, including Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic for the system, a single fault in the inter-processor Network-on-Chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this paper, we develop critical path models for HCI- and NBTI-induced wear due to the actual stresses caused by real workloads, applied onto the interconnect microarchitecture. A key finding from this modeling being that, counter to prevailing wisdom, wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. We then develop a novel wearout-decelerating scheme in which routers under low load have their wearout-sensitive components exercised, without significantly impacting cycle time, pipeline depth, area or power consumption of the overall router. We subsequently show that the proposed design yields a 13.8x-65x increase in CMP lifetime.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.publisherACMen_US
dc.rights© 2013 ACM.en_US
dc.subjectHot carrier injection (HCI)en_US
dc.subjectLifetimeen_US
dc.subjectNetwork-on-chipen_US
dc.subjectWearouten_US
dc.subjectNegative bias temperature instability (NBTI)en_US
dc.titleUse it or lose it: Wear-out and lifetime in future chip multiprocessorsen_US
dc.typeConference Papersen_US
dc.collaborationTexas AandM Universityen_US
dc.collaborationCyprus University of Technologyen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.countryUnited Statesen_US
dc.countryCyprusen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.relation.conferenceAnnual IEEE/ACM International Symposium on Microarchitectureen_US
dc.identifier.doi10.1145/2540708.2540721en_US
cut.common.academicyear2013-2014en_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.cerifentitytypePublications-
item.openairetypeconferenceObject-
item.languageiso639-1en-
item.openairecristypehttp://purl.org/coar/resource_type/c_c94f-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0002-2818-0459-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
Appears in Collections:Δημοσιεύσεις σε συνέδρια /Conference papers - poster -presentation
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