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Title: Optimising the SHA-512 cryptographic hash function on FPGAs
Authors: Athanasiou, George S. 
Michail, Harris 
Theodoridis, George 
Goutis, Costas E. 
Keywords: Hash functions;Pipeline processing systems;Pipelines;Timing circuits
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: 1-Jan-2014
Publisher: Institution of Engineering and Technology
Source: IET Computers and Digital Techniques, vol. 8, no. 2, 2014, pp. 70-82
DOI: 10.1049/iet-cdt.2013.0010
Journal: IET Computers and Digital Techniques 
Abstract: In this study, novel pipelined architectures, optimised in terms of throughput and throughput/area factors, for the SHA-512 cryptographic hash function, are proposed. To achieve this, algorithmic- and circuit-level optimisation techniques such as loop unrolling, re-timing, temporal pre-computation, resource re-ordering and pipeline are applied. All the techniques, except pipeline are applied in the function's transformation round. The pipeline was applied through the development of all the alternative pipelined architectures and implementation in several Xilinx FPGA families and they are evaluated in terms of frequency, area, throughput and throughput/area factors. Compared to the initial un-optimised implementation of SHA-512 function, the introduced five-stage pipelined architecture improves the both the throughput and throughput/area factors by 123 and 61.5%, respectively. Furthermore, the proposed five-stage pipelined architecture outperforms the existing ones both in throughput (3.4× up to 16.9×) and throughput/area (19.5% up to 6.9×) factors.
ISSN: 1751-8601
DOI: 10.1049/iet-cdt.2013.0010
Rights: © The Institution of Engineering and Technology 2014.
Type: Article
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