Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/9346
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dc.contributor.authorMichail, Harris-
dc.contributor.authorAthanasiou, George S.-
dc.contributor.authorTheodoridis, George-
dc.contributor.authorGregoriades, Andreas-
dc.contributor.authorGoutis, Costas E.-
dc.contributor.otherΜιχαήλ, Χάρης-
dc.contributor.otherΓρηγοριάδης, Ανδρέας-
dc.date.accessioned2017-01-31T12:50:37Z-
dc.date.available2017-01-31T12:50:37Z-
dc.date.issued2016-09-
dc.identifier.citationMicroprocessors and Microsystems, 2016, vol. 45, pp. 227-240en_US
dc.identifier.issn0141-9331-
dc.description.abstractMany cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec and VPN's utilize hash functions - a special family of cryptographic algorithms. Hardware implementations of cryptographic hash functions provide high performance and increased security. However, potential faults during their normal operation cause significant problems in the authentication procedure. Hence, the on-time detection of errors is of great importance, especially when they are used in security-critical applications, such as military or space. In this paper, two Totally Self-Checking (TSC) designs are introduced for the two most-widely used hash functions: SHA-1 and SHA-256. To the best of authors’ knowledge, there is no previously published work presenting TSC hashing cores. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even erroneous bits, if they are appropriately spread. Additionally, experimental results in terms of frequency, area, throughput, and power consumption are provided. Compared to the corresponding Duplicated with Checking (DWC) architectures, the proposed TSC-based designs are more efficient in terms of area, throughput/area, and power consumption. Specifically, the introduced TSC SHA-1 and SHA-256 cores are more efficient by 16.1% and 20.8% in terms of area and by 17.7% and 23.3% in terms of throughput/area, respectively. Also, compared to the corresponding DWC architectures, the proposed TSC-based designs are on average almost 20% more efficient in terms of power consumption.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.publisherElsevieren_US
dc.relation.ispartofMicroprocessors and Microsystemsen_US
dc.rights© 2016 Elsevier B.V.en_US
dc.subjectConcurrent Error Detectionen_US
dc.subjectCryptographyen_US
dc.subjectHash functionsen_US
dc.subjectSHA-1en_US
dc.subjectSHA-256en_US
dc.subjectTotally Self-Checkingen_US
dc.titleDesign and implementation of totally-self checking SHA-1 and SHA-256 hash functions’ architecturesen_US
dc.typeArticleen_US
dc.doihttp://dx.doi.org/10.1016/j.micpro.2016.05.011en_US
dc.collaborationCyprus University of Technologyen_US
dc.collaborationUniversity of Patrasen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.journalsSubscription Journalen_US
dc.countryCyprusen_US
dc.countryGreeceen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1016/j.micpro.2016.05.011en_US
cut.common.academicyear2016-2017en_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.languageiso639-1other-
crisitem.journal.journalissn0141-9331-
crisitem.journal.publisherElsevier-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Hotel and Tourism Management-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Management and Economics-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Management and Economics-
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