Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/9237
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dc.contributor.authorKakoulli, Elena-
dc.contributor.authorSoteriou, Vassos-
dc.contributor.authorKoutsides, Charalambos-
dc.contributor.authorKalli, Kyriacos-
dc.contributor.otherΚακουλλή, Έλενα-
dc.contributor.otherΣωτηρίου, Βάσος-
dc.contributor.otherΚαλλή, Κυριάκος-
dc.contributor.otherΚουτσίδης, Χαράλαμπος-
dc.date.accessioned2017-01-25T13:33:43Z-
dc.date.available2017-01-25T13:33:43Z-
dc.date.issued2017-06-
dc.identifier.citationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, vol. 36 , no. 6, pp. 978 - 991en_US
dc.identifier.issn0278-0070-
dc.description.abstractOn-chip nanophotonics offer high throughput, yet energy-efficient communication, traits that can prove critical to the continuance of multicore chip scalability. In this paper we investigate and propose silicon nanophotonic components that are embedded entirely in the silica (SiO2) substrate, i.e., reside subsurface, as opposed to die on-surface silicon nanophotonics of prior-art. Among several offered advantages, such Siliconin-Silica (SiS) nanophotonic structures empower the implementation of non-obstructive interconnect geometries that deliver an improved power-performance balance, as demonstrated experimentally. First, using exhaustive simulations based on commercial-grade optical software-based tools, we show that such SiS structures are feasible, and derive their geometry characteristics and design parameters. As a second step, utilizing SiS optical channels and filters, we then design two distinct SiS-based nanoPhotonic Network-on-Chip (PNoC) mesh-diagonal links topologies as a means of demonstrating our proof of concept. In further pushing the performance envelope, we next develop (1) an associated contention-aware adaptive routing function, and (2) a parallelized photonic channel allocation scheme, with both coupled to SiS-based PNoCs as elements, to respectively replace under-performing routing and flow-control photonic protocols currently utilized. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multiprocessor simulations, shows that our methodology boosts network throughput by up to 59:7%, reduces communication latency by up to 78:7%, while improving the throughput-to-power ratio by up to 31:6% when compared to the state-of-the-art.en_US
dc.formatpdfen_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.relation.ispartofIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
dc.rights© 2016 IEEE.en_US
dc.subjectAdaptive Routing Algorithmen_US
dc.subjectFlow-Controlen_US
dc.subjectNanophotonic Network-on-Chipen_US
dc.subjectSilicon-in-Silicaen_US
dc.subjectTopologyen_US
dc.titleSilica-Embedded Silicon Nanophotonic On-Chip Networksen_US
dc.typeArticleen_US
dc.collaborationCyprus University of Technologyen_US
dc.subject.categoryElectrical Engineering - Electronic Engineering - Information Engineeringen_US
dc.journalsSubscription Journalen_US
dc.countryCyprusen_US
dc.subject.fieldEngineering and Technologyen_US
dc.publicationPeer Revieweden_US
dc.identifier.doi10.1109/TCAD.2016.2611516en_US
cut.common.academicyear2016-2017en_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.languageiso639-1other-
crisitem.journal.journalissn0278-0070-
crisitem.journal.publisherIEEE-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.deptDepartment of Electrical Engineering, Computer Engineering and Informatics-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.facultyFaculty of Engineering and Technology-
crisitem.author.orcid0000-0003-1489-807X-
crisitem.author.orcid0000-0002-2818-0459-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
crisitem.author.parentorgFaculty of Engineering and Technology-
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