Please use this identifier to cite or link to this item:
Title: Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects
Authors: Vitkovskiy, Arseniy 
Soteriou, Vassos 
Gratz, Paul V. 
Keywords: Human computer interaction;Transistors;Routing;Stress;Electromigration;Correlation;Integrated circuit interconnections
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: 14-Dec-2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: 33rd IEEE International Conference on Computer Design, ICCD 2015; New York City; United States; 18- 21 October 2015
Conference: IEEE International Conference on Computer Design, ICCD 
Abstract: With advancing process technology, Chip-Multiprocessors (CMPs) are experiencing ever worsening reliability due to prolonged operational stresses. The network-on-chip that interconnects the components of CMPs is especially vulnerable to such wearout-induced failure. To tackle this ominous threat we present Clotho, a novel, wearout-Aware routing algorithm. Clotho continuously considers the stresses the on-chip interconnect experiences at runtime, along with temperature and fabrication process variation metrics, steering traffic away from locations that are most prone to Electromigration (EM)-and Hot-Carrier Injection (HCI)-induced wear. Under realistic workloads Clotho yields 66% and 8% average increases in mean time to failure for EM and HCI, respectively.
ISBN: 978-146737165-0
DOI: 10.1109/ICCD.2015.7357092
Rights: © 2015 IEEE.
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

Show full item record

Page view(s)

Last Week
Last month
checked on Jun 24, 2019

Google ScholarTM



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.