Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/9129
Title: Design of high-performance, power-efficient optical NoCs using Silica-embedded silicon nanophotonics
Authors: Kakoulli, Elena 
Soteriou, Vassos 
Koutsides, Charalambos 
Kalli, Kyriacos 
Keywords: Optical waveguides;Nanophotonics;Silicon;Optical refraction;Optical variables control
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: 14-Dec-2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: (2015) Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015, art. no. 7357077, pp. 1-8
Conference: IEEE International Conference on Computer Design, ICCD 
Abstract: With on-chip electrical interconnects being marred by high energy-To-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high throughput, yet energy-efficient communication, form an alternative attractive counterpart. In this paper we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to prior-Art that utilizes die on-surface silicon nanophotonics. As nanophotonic components now reside in the silica substrate's subsurface non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial optical tools that such Silicon-In-Silica (SiS) structures are feasible, derive their geometry characteristics and design parameters, and then demonstrate our proof of concept by utilizing a hybrid SiS-based photonic mesh-diagonal links network-on-chip topology. In pushing the performance envelope even more, we next develop (1) an associated contention-Aware photonic adaptive routing function, and (2) a parallelized photonic channel allocation scheme, that in tandem further reduce message delivery latency. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multiprocessor simulations, shows that our methodology boosts network throughput by up to 30.8%, reduces communication latency by up to 22.5%, and improves the throughput-To-power ratio by up to 23.7% when compared to prior-Art.
ISBN: 978-146737165-0
DOI: 10.1109/ICCD.2015.7357077
Rights: © 2015 IEEE.
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

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