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Title: Speeded up and low-powered hardware implementation of the secure hash algorithm through partial unrolling
Authors: Michail, Harris 
Kakarountas, Athanasios P. 
Theodoridis, Georgios A. 
Keywords: Algorithms;Electronic commerce;Data integrity;Hardware
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: Jul-2005
Publisher: WSEAS
Source: WSEAS Transactions on Computers, 2005, vol. 4, no. 7, pp. 814-821
Journal: WSEAS Transactions on Computers 
Abstract: Applications that call for data integrity and signature authentication at electronic transactions invoke cryptographic primitives like hash functions. A hash function is utilized in the security layer of every communication protocol. However, as protocols evolve and new high-performance applications appear, the throughput of hash functions seems to reach to a limit. Market is asking for new implementations with higher throughputs respecting the tendency of the market to minimize devices' size and increase their autonomy to make them portable. The existing SHA-1 Hash Function implementations (SHA-1 is common in many protocols e.g. IPSec) limit throughput to a maximum of 2 Gbps. In this paper, a new a partially unrolled implementation is presented that comes to exceed this limit improving the throughput by 53%. Power issues have also been taken in consideration, in such way that the proposed implementation can be characterized as low-power.
ISSN: 1109-2750
Collaboration : University of Patras
Aristotle University of Thessaloniki
Rights: © WSEAS
Type: Article
Appears in Collections:Άρθρα/Articles

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