Please use this identifier to cite or link to this item:
|Title:||Design and implementation of a SHA-3 candidate Skein-512 hash/MAC hardware architecture||Authors:||Michail, Harris
Athanasiou, George S.
Tsingkas, Elias N.
Chalkou, Chara I.
Goutis, Costas E.
|Keywords:||Cryptography;Algorithms;Hardware||Category:||Electrical Engineering - Electronic Engineering - Information Engineering||Field:||Engineering and Technology||Issue Date:||Mar-2012||Publisher:||IEEE||Source:||2012 IEEE International Conference on Industrial Technology, ICIT 2012, Proceedings, art. no. 6209998, pp. 561-566; 2012 IEEE International Conference on Industrial Technology, ICIT 2012; Athens; Greece; 19 March 2012 through 21 March 2012||Conference:||IEEE International Conference on Industrial Technology||Abstract:||Many cryptographic primitives that are used in crucial cryptographic schemes and commercial security protocols utilize hash functions. Recently, the National Institute of Standards and Technology (NIST) launched an international competition for establishing the new hash standard, SHA-3. One of the semifinalists is the Skein algorithm. In this paper, an 8-round unrolled architecture of the complete Skein algorithm is presented, implemented in Xilinx Spartan-3 and Virtex-5 FPGAs. The design is able to perform both as simple Hash and MAC module. The performance metrics, such as Frequency and Area, that are gathered, show that the proposed implementation is more efficient in terms of Throughput/Area, compared to other similar ones, proposed by academia.||ISBN:||978-146730342-2||DOI:||10.1109/ICIT.2012.6209998||Rights:||© 2012 IEEE||Type:||Conference Papers|
|Appears in Collections:||Κεφάλαια βιβλίων/Book chapters|
Show full item record
checked on Aug 26, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.