Please use this identifier to cite or link to this item:
Title: A methodology for speeding up fast fourier transform focusing on memory architecture utilization
Authors: Michail, Harris 
Kelefouras, Vasileios I. 
Athanasiou, George S. 
Alachiotis, Nikolaos 
Kritikakou, Angeliki S. 
Goutis, Costas E. 
Keywords: Cache memory;Embedded computer systems;Multiplication;Compilers (Computer programs)
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: Dec-2011
Publisher: IEEE
Source: IEEE Transactions on Signal Processing, 2011, vol. 59, no. 12, pp. 6217-6226
Journal: IEEE Transactions on Signal Processing 
Abstract: Several SOA (state of the art) self-tuning software libraries exist, such as the Fastest Fourier Transform in the West (FFTW) for fast Fourier transform (FFT). FFT is a highly important kernel and the performance of its software implementations depends on the memory hierarchy's utilization. FFTW minimizes register spills and data cache accesses by finding a schedule that is independent of the number of the registers and of the number of levels and size of the cache, which is a serious drawback. In this paper, a new methodology is presented, achieving improved performance by focusing on memory hierarchy utilization. The proposed methodology has three major advantages. First, the combination of production and consumption of butterflies' results, data reuse, FFT parallelism, symmetries of twiddle factors and also additions by zeros and multiplications by zeros and ones when twiddle factors are zero or one, are fully and simultaneously exploited. Second, the optimal solution is found according to the number of the registers, the data cache sizes, the number of the levels of data cache hierarchy, the main memory page size, the associativity of the data caches and the data cache line sizes, which are also considered simultaneously and not separate. Third, compilation time and source code size are very small compared with FFTW. The proposed methodology achieves performance gain about 40% (speed-up of 1.7) for architectures with small data cache sizes where memory management has a larger effect on performance and 20% (speed-up of 1.25) on average for architectures with large data cache sizes (Pentium) in comparison with FFTW.
ISSN: 1053-587X
DOI: 10.1109/TSP.2011.2168525
Rights: © 2011 IEEE
Type: Article
Appears in Collections:Άρθρα/Articles

Show full item record


checked on Apr 21, 2019


checked on Aug 21, 2019

Page view(s)

Last Week
Last month
checked on Aug 24, 2019

Google ScholarTM



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.