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|Title:||On the exploitation of a high-throughput SHA-256 FPGA design for HMAC||Authors:||Michail, Harris
Athanasiou, George S.
|Keywords:||Mathematical optimization;Field programmable gate arrays;Computer networks--Security measures||Issue Date:||2012||Publisher:||ACM||Source:||ACM Transactions on Reconfigurable Technology and Systems, 2012, Volume 5, Issue 1||Abstract:||High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board).||URI:||http://ktisis.cut.ac.cy/handle/10488/7303||ISSN:||19367406||DOI:||10.1145/2133352.2133354||Rights:||© 2012 ACM||Type:||Article|
|Appears in Collections:||Άρθρα/Articles|
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