Please use this identifier to cite or link to this item:
Title: A fine-grained link-level fault-tolerant mechanism for networks-on-chip
Authors: Vitkovskiy, Arseniy 
Nicopoulos, Chrysostomos 
Soteriou, Vassos 
Keywords: Computer science;Computer architecture;Hardware;Networks on a chip;Fault tolerant computing;Microprocessors;Computer network architectures;Routers (Computer networks)
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: 2010
Publisher: IEEE Xplore
Source: 2010 IEEE International conference on computer design (ICCD), pp. 447-454
Conference: IEEE International Conference on Computer Design, ICCD 
Abstract: Silicon technology scaling is continuously enabling denser integration capabilities. However, this comes at the expense of higher variability and susceptibility to wear-out. With an escalating number of on-chip components expected to be defective in near-future chips, modern parallel systems, such as Chip Multi-Processors (CMP), become especially vulnerable to these faults. Just a single link failure in the underlying Network on-Chip (NoC) may cause inter-tile communication to halt and even deadlock, rendering the chip useless. While fault-tolerant routing schemes do exist, they can only handle a finite number of link faults. In this paper, we address permanent wire failures which can occur in on-chip parallel links at manufacture-time or while in operation. Instead of marking the entire link as faulty, we present a methodology where the Partially Faulty Link (PFL) can still be used to transfer data between NoC routers, thus maintaining network connectivity, extending the yield and lifetime of the chip, and allowing for graceful performance degradation. To achieve this, we devise architectural augmentations both to the router and link micro-architectures, along with link fault detection, diagnosis, and re-configuration at the level of wire granularity. Statistical link-level fault models present the usability of PFLs, while relevant load-balancing routing algorithms and low-cost re-transmission mechanisms are also presented and coupled to the proposed architecture. Hardware synthesis demonstrates the feasibility of the proposed extensions to the base NoC architecture. Results obtained from full-system simulations show that high-performance NoCs are realizable in the presence of PFLs
URI: 1063-6404
ISBN: 978-1-4244-8935-0
DOI: 10.1109/ICCD.2010.5647663
Rights: © Copyright 2010 IEEE
Type: Conference Papers
Appears in Collections:Κεφάλαια βιβλίων/Book chapters

Show full item record


checked on Apr 20, 2019

Page view(s)

Last Week
Last month
checked on Oct 14, 2019

Google ScholarTM



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.