Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/13416
Title: Optimisation and Simulation of RC Time Constants in Snubber Circuits
Authors: Mohanram, Sat 
Darwish, Mohamed 
Marouchos, Christos 
Keywords: Hard switching;Input-output parameters;Simulation;Snubber Circuit (RC);Switching frequency;Losses;TC Optimizations
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: Nov-2018
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: 53rd International Universities Power Engineering Conference, 2018, 4-7 September, Glasgow, United Kingdom;
Conference: International Universities Power Engineering Conference 
Abstract: Semiconductor devices are subjected to elevated levels of stresses when used at high voltage high current and temperature applications. This stress is mainly due to hard switching which is proportional to the switching frequency. This paper presents methods used to remove this energy to prevent expensive switch damage due to overheating and high dv/dt oscillations. In confirmation of the research title, the process in the determination of 'RC' in snubber circuits has been proven by OrCAD optimisation and presented.
URI: http://ktisis.cut.ac.cy/handle/10488/13416
DOI: 10.1109/UPEC.2018.8542111
Rights: © 2018 IEEE.
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

Show full item record

Page view(s)

31
Last Week
1
Last month
4
checked on Nov 20, 2019

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.