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|Title:||Simulation of the electrical characteristics of MOS capacitors on strained-silicon substrates||Authors:||Kelaidis, N.
|Issue Date:||2008||Publisher:||WILEY-VCH Verlag GmbH & Co.||Source:||physica status solidi (c), Volume 5 Issue 12, Pages 3647 - 3650||Abstract:||In this work, we analyze the electrical characteristics of MOS capacitors fabricated on strained silicon substrates using the commercial software Taurus/Synopsis. The effect of various parameters such as Germanium concentration in the Si1-xGex virtual substrate, thickness of the strained-Silicon layer, oxide thickness, fixed charge and interface trapped charge on capacitance - voltage characteristics is examined. Experimental data are compared with simulation results. A strong influence of the s-Si/SiGe heterostructure and its proximity to the s-Si/SiO2 on the electrical characteristics of the system exists. Oxide charge inserted into simulation in order to fit experimental data shows an increase of charge with decreasing s-Si thickness. The effect of interface traps on simulated C-V characteristics is identical when traps are situated in the s-Si/SiO2 or the s-Si/SiGe interface. When increasing the thermal budget by increasing the post oxidation annealing time, the decrease of the hump phenomenon on the C-V curves can be attributed to the Germanium diffusion, according to simulation.||URI:||http://ktisis.cut.ac.cy/handle/10488/1116||DOI:||10.1002/pssc.200780207||Rights:||© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim||Type:||Article|
|Appears in Collections:||Άρθρα/Articles|
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