Please use this identifier to cite or link to this item: https://ktisis.cut.ac.cy/handle/10488/10981
Title: Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis
Authors: Kalli, Kyriacos 
Deliparaschos, Kyriakos M. 
Moustris, George P. 
Georgiou, Avraam 
Charalambous, Themistoklis 
Keywords: Delaunay triangulation;Field programmable gate array;High-level synthesis;Pipelining;Register- Transfer-level;Surface reconstruction
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: 12-Sep-2017
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: 22nd IEEE International Conference on Emerging Technologies and Factory Automation, 2017, Limassol, Cyprus, 12-15 September
Conference: IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 
Abstract: This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.
DOI: 10.1109/ETFA.2017.8247736
Rights: © 2017 IEEE.
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

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