Please use this identifier to cite or link to this item:
https://hdl.handle.net/20.500.14279/9366| Title: | High performance pipelined FPGA implementation of the SHA-3 hash algorithm | Authors: | Ioannou, Lenos Michail, Harris Voyiatzis, Artemios G. |
metadata.dc.contributor.other: | Ιωάννου, Λένος Μιχαήλ, Χάρης |
Major Field of Science: | Engineering and Technology | Field Category: | Electrical Engineering - Electronic Engineering - Information Engineering | Keywords: | FPGA;Hash algorithm;High performance;Pipeline;SHA-3 | Issue Date: | 6-Aug-2015 | Source: | (2015) Proceedings - 4th Mediterranean Conference on Embedded Computing, MECO 2015 - Including ECyPS 2015, BioEMIS 2015, BioICT 2015, MECO-Student Challenge 2015, art. no. 7181868, pp. 68-71; 4th Mediterranean Conference on Embedded Computing, MECO 2015, Budva, Montenegro, 14 June 2015 through 18 June 2015 | Conference: | Mediterranean Conference on Embedded Computing | Abstract: | The SHA-3 cryptographic hash algorithm is standardized in FIPS 202. We present a pipelined hardware architecture supporting all the four SHA-3 modes of operation and a high-performance implementation for FPGA devices that can support both multi-block and multi-message processing. Experimental results on different FPGA devices validate that the proposed design achieves significant throughput improvements compared to the available literature. | ISBN: | 978-147998999-7 | DOI: | 10.1109/MECO.2015.7181868 | Rights: | © 2015 IEEE. | Type: | Conference Papers | Affiliation : | Cyprus University of Technology SBA Research Vienna |
| Appears in Collections: | Δημοσιεύσεις σε συνέδρια /Conference papers or poster or presentation |
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