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https://hdl.handle.net/20.500.14279/13933| Title: | Implementation of HSSec: A high-speed cryptographic co-processor | Authors: | Kakarountas, A. P. Goutis, C. E. Michail, Harris Efstathiou, C. |
Major Field of Science: | Engineering and Technology | Field Category: | Electrical Engineering - Electronic Engineering - Information Engineering | Keywords: | Cryptographic primitives;Hash Functions | Issue Date: | 1-Dec-2007 | Source: | (2007) IEEE International Conference on Emerging Technologies and Factory Automation, ETFA, art. no. 4416827, pp. 625-631 | Conference: | IEEE International Conference on Emerging Technologies and Factory Automation, ETFA | Abstract: | In this paper a high-speed cryptographic co-processor, named HSSec, is presented. The core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES. The architecture of HSSec renders it suitable for widely spread applications with security demands. The presented co-processor can be used inevery system integrating standards such as IPSec or the upcoming JPSec and P1619. The main characteristic of the proposed implementation is common use of the available resources, to minimize further area requirements. Additionally the cryptographic primitives can operate in parallel, providing high throughput whenever needed. Finally the system can operate in ECB or CBC modes. The HSSec co-processor has relatively small area and its performance reaches 1 Gbps (AES, SHA-1 and SHA-512) for XILINX's Virtex II FPGA family. © 2007 IEEE. | ISBN: | 978-142440826-9 | DOI: | 10.1109/EFTA.2007.4416827 | Rights: | © 2007 IEEE | Type: | Conference Papers | Affiliation : | University of Patras University of West Attica |
| Appears in Collections: | Δημοσιεύσεις σε συνέδρια /Conference papers or poster or presentation |
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