Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/9969
Title: Use it or lose it: Proactive, deterministic longevity in future chip multiprocessors
Authors: Kim, Hyungjun 
Boga, Siva Bhanu Krishna 
Vitkovskiy, Arseniy 
Hadjitheophanous, Stavros 
Gratz, Paul V. 
Soteriou, Vassos 
Michael, Maria K. 
Keywords: Hot-carrier injection (HCI);Lifetime;Negative-bias temperature instability (NBTI);Network-on-chip;Reliability;Wearout
Category: Computer and Information Sciences
Field: Natural Sciences
Issue Date: 1-Jan-2015
Publisher: Association for Computing Machinery
Source: ACM Transactions on Design Automation of Electronic Systems, 2015, Volume 20, Issue 4, Article number A65
metadata.dc.doi: 10.1145/2770873
Abstract: Moore's Law scaling continues to yield higher transistor density with each succeeding process generation, leading to today'smany-core chip multiprocessors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep submicron CMOS process technology is marred by increasing susceptibility to wear. Prolonged operational stress gives rise to accelerated wearout and failure due to several physical failure mechanisms, including hot-carrier injection (HCI) and negative-bias temperature instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic, a single fault in the interprocessor network-on-chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this article, we study HCI- and NBTI-induced wear due to actual stresses caused by real workloads, applied onto the interconnect microarchitecture and develop a critical path model for NBTI-induced wearout. A key finding of this modeling is that, counter to prevailing wisdom, wearout in the CMP's on-chip interconnect is correlated with lack of load observed in the NoC routers rather than high load. We then develop a novel wearout-decelerating scheme in which routers under low load have their wear-sensitive components exercised without significantly impacting cycle time, pipeline depth, area, or power consumption of the overall router. A novel deterministic approach is proposed for the generation of appropriate exercise-mode data, ensuring design parameter targets are met. We subsequently show that the proposed design yields an ∼2,300× decrease in the rate of wear.
URI: http://ktisis.cut.ac.cy/handle/10488/9969
ISSN: 10844309
Rights: © 2015 ACM.
Type: Article
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