Please use this identifier to cite or link to this item:
|Title:||On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs||Authors:||Michail, Harris
Athanasiou, George S.
Goutis, Costas E.
|Keywords:||Authentication;FPGA;Hash;Multi-mode||Category:||Computer and Information Sciences||Field:||Natural Sciences||Issue Date:||1-Jan-2014||Publisher:||Elsevier Ltd||Source:||Integration, the VLSI Journal Volume 47, Issue 4, September 2014, Pages 387-407||metadata.dc.doi:||http://dx.doi.org/10.1016/j.vlsi.2014.02.004||Abstract:||In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.||URI:||http://ktisis.cut.ac.cy/handle/10488/9849||ISSN:||01679260||Rights:||© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.||Type:||Article|
|Appears in Collections:||Άρθρα/Articles|
Show full item record
Page view(s) 5070
checked on Dec 18, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.