Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/9817
Title: High-performance FPGA implementations of the cryptographic hash function JH
Authors: Athanasiou, George S. 
Michail, Harris 
Theodoridis, G. 
Goutis, Costas E. 
Keywords: Authentication services
Cryptographic hash functions
Cryptographic schemes
Design alternatives
FPGA implementations
International competitions
Pipelined architecture
Security protocols
Issue Date: 31-Jul-2013
Publisher: Institution of Engineering and Technology
Source: IET Computers and Digital Techniques, 2013, Volume 7, Issue 1, Pages 29-40
Abstract: Hash functions are included in almost all cryptographic schemes and security protocols for providing authentication services. JH is a new hash function, introduced in 2008 and it is among the five finalists of the international competition for developing the new hash standard SHA-3. In this study, one non-pipelined and four pipelined architectures are introduced for developing high-performance field-programmable gate array (FPGA) designs of the JH function. Special effort has been paid and various design alternatives have been studied to derive efficient FPGA implementations in terms of frequency, area and throughput/ area cost factor. Compared with the best existing non-pipelined FPGA implementations, the throughput/area is improved by 48, 13.5 and 17.8% in Xilinx Virtex-4, Virtex-5 and Virtex-6 families, respectively, and by 6.8 and 21.2% in ALTERA Stratix-III and Stratix-IV, respectively. Also, the improvements of the throughput/area factor of the introduced pipelined architectures over the existing ones are 37.5, 73.1, 15 and 26.3% in Virtex-5, Virtex-6, Stratix-III and Stratix-IV technologies, respectively.
URI: http://ktisis.cut.ac.cy/handle/10488/9817
ISSN: 17518601
Rights: © The Institution of Engineering and Technology 2013.
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