Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/9815
Title: Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths
Authors: Vitkovskiy, Arseniy 
Soteriou, Vassos 
Nicopoulos, Chrysostomos 
Keywords: Complementary metal oxide semiconductors;Distributed decision;Fault-tolerant routing algorithm;Full-system simulation;Integration density;Networks on chips;On chip communication;Real applications
Category: Computer and Information Sciences
Field: Engineering and Technology
Issue Date: 31-Jul-2013
Publisher: Institution of Engineering and Technology
Source: IET Computers and Digital Techniques, 2013, Volume 7, Issue 2, Pages 93-103
metadata.dc.doi: 10.1049/iet-cdt.2012.0054
Abstract: Downscaled complementary metal-oxide semiconductor (CMOS) technology feature sizes have enabled massive transistor integration densities. Multi-core chips with billions of transistors are now a reality. However, this rapid increase in on-chip resources has come at the expense of higher susceptibility to defects and wear-out. The inter-router communication links of networks-on-chips (NoCs) are composed of metal wires that are especially vulnerable to catastrophic physical effects such as those of electro-migration, which can even cause link disconnects. To address this hazard, fault-tolerant (FT) routing algorithms sustain on-chip communication by re-routing messages around faulty links, or regions. This work presents a new FT routing scheme that employs a localised re-routing approach. Packets are de-toured around faulty links/regions based on purely local and distributed decisions, and without any global link state knowledge. The algorithm, which is proven to be deadlock-and livelock-free, also handles dynamically occurring faults. Detailed evaluation with synthetic traffic patterns and real applications within a full-system simulation environment demonstrate the efficacy of the new scheme with up to 12% of NoC links being faulty. Synthesis results also prove the feasibility of the proposed protocol at modest hardware and power consumption overheads of only over 5 and 2.5%, respectively.
URI: http://ktisis.cut.ac.cy/handle/10488/9815
ISSN: 17518601
Rights: © The Institution of Engineering and Technology 2013.
Type: Article
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