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|Title:||Hermes: Architecting a top-performing fault-tolerant routing algorithm for networks-on-chips||Authors:||Iordanou, Costas
|Keywords:||Algorithms;Microprocessor chips;Network architecture;Program compilers;Routing algorithms||Category:||Computer and Information Sciences||Field:||Natural Sciences||Issue Date:||1-Jan-2015||Publisher:||Institute of Electrical and Electronics Engineers Inc.||Source:||8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014; Ferrara; Italy; 17 September 2014 through 19 September 2014||metadata.dc.doi:||10.1109/NOCS.2014.7008782||Abstract:||Networks-on-Chips (NoCs) are experiencing escalating susceptibility to wear-out and reduced reliability, with the risk of becoming the key point of failure in an entire multicore chip. In this paper we propose Hermes, a highly-robust, distributed fault-tolerant routing algorithm, whose performance degrades gracefully with increasing faulty NoC link counts. Hermes is a deadlock-free hybrid routing algorithm, utilizing load-balanced routing on fault-free paths, while providing pre-reconfigured escape routes in the vicinity of faults. An initial experimental evaluation shows that Hermes improves network throughput by up to 2.2× when compared against the existing state-of-the-art.||URI:||http://ktisis.cut.ac.cy/handle/10488/9515||ISBN:||978-147995347-9||Rights:||© 2014 IEEE.||Type:||Conference Papers|
|Appears in Collections:||Δημοσιεύσεις σε συνέδρια/Conference papers|
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