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|Title:||High performance pipelined FPGA implementation of the SHA-3 hash algorithm||Authors:||Ioannou, Lenos
Voyiatzis, Artemios G.
|Keywords:||FPGA;Hash algorithm;High performance;Pipeline;SHA-3||Category:||Electrical Engineering - Electronic Engineering - Information Engineering||Field:||Engineering and Technology||Issue Date:||6-Aug-2015||Source:||4th Mediterranean Conference on Embedded Computing, MECO 2015; Budva; Montenegro; 14 June 2015 through 18 June 2015||metadata.dc.doi:||10.1109/MECO.2015.7181868||Abstract:||The SHA-3 cryptographic hash algorithm is standardized in FIPS 202. We present a pipelined hardware architecture supporting all the four SHA-3 modes of operation and a high-performance implementation for FPGA devices that can support both multi-block and multi-message processing. Experimental results on different FPGA devices validate that the proposed design achieves significant throughput improvements compared to the available literature.||URI:||http://ktisis.cut.ac.cy/handle/10488/9366||ISBN:||978-147998999-7||Rights:||© 2015 IEEE.||Type:||Conference Papers|
|Appears in Collections:||Δημοσιεύσεις σε συνέδρια/Conference papers|
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