Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/9353
Title: Designing high-performance, power-efficient NoCs with embedded silicon-in-silica nanophotonics
Authors: Kakoulli, Elena 
Soteriou, Vassos 
Koutsides, Charalambos 
Kalli, Kyriacos 
Keywords: On-chip nanophotonics;Silicon-in-silica;Topology
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: 28-Sep-2015
Publisher: Association for Computing Machinery, Inc
Source: 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015; Vancouver; Canada; 28 September 2015 through 30 September 2015
metadata.dc.doi: 10.1145/2786572.2786588
Abstract: On-chip electrical links exhibit large energy-to-bandwidth costs, whereas on-chip nanophotonics, which attain high throughput, yet energy-efficient communication, have emerged as an alternative interconnect in multicore chips. Here we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to existing die on-surface silicon nanophotonics. As nanophotonic components now reside subsurface, within the silica substrate, non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such Silicon-in-Silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a SiS-based mesh-interconnected topology with augmented diagonal optical channels that provides both higher effective throughput and throughput-to-power ratio versus prior-art.
URI: http://ktisis.cut.ac.cy/handle/10488/9353
ISBN: 978-145033396-2
Rights: Copyright is held by the owner/author(s).
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

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